In the manufacture of transistors having a polysilicon emitter structure a thin interfacial oxide layer is formed between an underlying substrate of single crystal silicon (“monocrystalline silicon”) and an upper layer of polycrystalline silicon (“polysilicon”). The presence of the interfacial oxide layer provides an increase in the current gain β of the transistor and generally improves the operation of the transistor. See, e.g., “The Role of the Interfacial Layer in Polysilicon Emitter Bipolar Transistors,” by A. A. Eltoukhy and D. J. Roulston in IEEE Transactions on Electron Devices, Volume 29, pp. 1862-1869 (1982).
For purposes of illustration, consider a portion of an exemplary prior art semiconductor device 100 shown in FIG. 1. Semiconductor device 100 comprises a monocrystalline silicon layer 110, an interfacial oxide layer 120, and a polysilicon emitter layer 130. During the manufacturing process of semiconductor device 100 the interfacial oxide layer 120 is formed on the underlying monocrystalline structure 110. Then the polysilicon emitter layer 130 is formed on the interfacial oxide layer 120.
The formation of an interfacial oxide is one of the critical manufacturing parameters for controlling current gain and emitter resistance in polysilicon emitter devices. The interfacial oxide may be formed from (1) native oxidation (oxide is grown in air at room temperature), (2) chemical oxidation (oxide is grown during a pre-clean process), (3) parasitic thermal oxidation (oxide is grown during initial heating of the wafers in the polysilicon deposition furnace), and (4) deliberate thermal oxidation (oxide is grown in the controlled environment of the polysilicon deposition furnace prior to the polysilicon deposition step). All four of the sources of oxidation mentioned above can contribute to the formation of the interfacial oxide layer. Great care must be taken to control each of the sources of oxidation in order to ensure the creation of an interfacial oxide layer that may be consistently repeated.
Several types of prior art methods have been employed to create an interfacial oxide layer. One of the earliest methods involved controlling (1) the rate at which wafers were pushed into a polysilicon furnace, (2) the temperature in the polysilicon furnace, and (3) the rate of inert purge gas flow in the polysilicon furnace. In this method the wafers at the pump end of the furnace load are heated longer than the wafers at the door end of the furnace. This creates an inherent difference in the interfacial oxide thickness in wafers at the two ends of the furnace.
In addition, changes in the relative humidity of the room can also make a very large difference in the oxidation rate. Some prior art attempts have been made to alleviate the contributions from the ambient atmosphere. Prior art devices have been attached to the mouth of the furnace tube to prevent the ambient atmosphere from reaching the wafers and from backstreaming into the furnace tube as the wafers are loaded. These devices are expensive, difficult to use, and have been known to create problems.
Another prior art method pre-oxidizes the wafer using a rapid thermal processing (RTP) step prior to the step of polysilicon deposition. The pre-oxidation step can be done either as a “stand alone” process or along with the deposition in the same RTP system. The rapid thermal processing allows for a very short oxidation time. Rapid thermal processing, however, only processes one wafer at a time. Therefore, in-situ deposition of the polysilicon (which can not be done very quickly) is impractical for single wafer processing. Adding a separate rapid thermal processing (RTP) step is undesirable because it adds handling, cycle time, capital equipment requirements, and more opportunities for creating scrap.
The amount of time between the rapid thermal processing (RTP) oxidation and the deposition of the polysilicon is critical because the interfacial oxide is grown very thin. If the oxide is given a chance to absorb moisture from the ambient atmosphere, further oxidation could occur as the wafers are pushed into the hot polysilicon deposition system. In addition, temperature control (and therefore control of the oxidation rate and the final interfacial oxide layer thickness) is much more difficult in a rapid thermal processing (RTP) step than in a furnace. This is because a furnace is a black body system.
Another prior art method for reducing the oxidation rate involves using dilute oxygen (O2). Unfortunately, maintaining a proper value of the oxygen partial pressure is very difficult. This is because any change in the oxygen or diluent will result in a change in the value of the oxygen partial pressure. For example, assume a gas flow of 0.3 LPM oxygen in a 9.7 LPM nitrogen. This arrangement represents a three percent (3%) oxygen (O2) atmosphere. If either or both of the gas flows change such that the ratio goes to a four percent (4%) oxygen atmosphere, this causes only a one percent (1%) absolute change but a twenty five percent (25%) change from the first value of oxygen to the second value of oxygen.
Another prior art method has involved the formation of a chemically grown oxide layer after the removal of the existing oxide but before the deposition of the polysilicon. This is usually done with a combination of ammonium hydroxide, hydrogen peroxide and water. This combination is sometimes referred to as an “RCA1” clean or “APM”. With this method the oxide thickness is sensitive not only to the initial chemical ratios, and the temperature of the solution, and the time in the solution, but also to the history of the bath. The active ingredients of the solution change over time and with use. Therefore, the active ingredients can be strongly affected by the contamination level on wafers that were run before the wafers that are targeted for critical oxide control.
Hydrogen termination in the pre-clean step can help reduce the formation of native oxide, and so reduce the sensitivity of the final oxide thickness to the time between the pre-clean and the polysilicon deposition. This is true for any of the prior art methods described above.
In view of the deficiencies of the prior art methods, there is a need for an efficient system and method that is capable of controlling the formation of an interfacial oxide in a polysilicon emitter transistor device. There is also a need in the art for an efficient system and method that is capable of precisely controlling the thickness of an interfacial oxide in a polysilicon emitter transistor device.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.